A FinFET transistor utilizes a channel region which is oriented to conduct an electrical current parallel to the surface of the substrate. The channel region is provided in an elongated section of semiconductor material referred to in the art as a “fin.” The source and drain regions of the transistor are typically also formed in or on the elongated section on each side of the channel region. A gate is placed over and on both opposed sides of the elongated section at the location of the channel region to provide control over the conductive state of the transistor. This FinFET design is well suited for manufacturing a multi-channel transistor in which multiple elongated sections are formed in parallel to define neighboring channel regions separated from each other by an intermediate gate portion, where the transistor gate spans with a perpendicular orientation over the multiple elongated sections.
Those skilled in the art understand the advantage of utilizing a silicon-germanium (SiGe) material for the formation of fins to be used in p-channel transistor devices. For example, SiGe material is preferred because it introduces compressive strain in the channel region of the transistor which results in improved mobility and device performance.
The amount of induced strain is, generally speaking, proportional to the level of germanium content within the SiGe fin material. It is recognized by those skilled in the art to provide as high a percentage of germanium as possible. For example, germanium content in excess of 25% is desired.
It is not technically difficult to produce silicon germanium semiconductor materials having a germanium content in excess of 25%. Well known epitaxial growth and thermal condensation techniques can be used to make such a material. The technical challenge, however, arises when attempting to shape the silicon germanium material into the fin of the FinFET device. The fabrication of the fin and the making of the FinFET device utilize a number of different etch and clean processes. Those skilled in the art recognize that the higher the germanium content of the silicon-germanium material, the more vulnerable that material may be to undesired consumption during fabrication processing. For example, the standard wet clean process (referred to by those skilled in the art as “SC1”) utilized in semiconductor manufacturing will consume silicon-germanium material at a faster rate relative to the germanium content proportion. This makes it difficult to maintain a consistent fin size, especially in comparison to the silicon material used for fin fabrication of n-channel devices located on the same wafer.
There is accordingly a need in the art for a method to support the fabrication of fins in FinFET devices made of silicon germanium with a relatively high (for example, greater than 25%) germanium content.